1. Field of the Invention
The present invention relates generally to memory systems and particularly to a non-volatile memory system having the capability of verifying programming operations using a reduced number of commands.
2. Description of Related Art
Non-volatile memory systems, including flash memory systems, have increased in popularity. Among other things, such memory systems have replaced hard disk drives as a primary memory resource in certain applications. Non-volatile memory systems of the flash variety contain memory cells that are initially erased to a "1" state, with the cells being selectively programmed to a "0"state during memory programming operations. As is well known, memory programming is carried out by application of appropriate voltages to the word and bit lines associated with the cell to be programmed. These programming voltages are effectively applied in the form of pulses, with the magnitude and duration of the pulses being such that multiple application of the pulses is required to complete the programming operation.
In a typical flash memory system, a programming operation includes a verification step to determine whether the cells to be programmed have been adequately programmed. This verification is similar to a read operation. In the event a cell has not been properly programmed, a further programming pulse is applied and the verification step repeated. In a typical programming operation, multiple cells are programmed. By way of example, assume that a byte of data is to be programmed with AAH (D0-D7=10101010). Since the cells are presumably in an initial erased state (11111111), only bits D1, D3, D5 and D7 will be programmed. Since all of the cells are not exactly the same, it is likely that at some point in the programming sequence one cell will be programmed before other cells are programmed. Continuing with the example, assume that a program verification indicates that bit D1 has been programmed but bits D3 D5 and D7 have not been programmed (10111111). In that event, at least one additional programming pulse will be needed. Such programming pulse will be applied only to the cells associated with bits D3, D5 and D7 and not cell associated with D0 since it is undesirable to over program cells.
It can be seen that several memory operations may be required in order to carry out a programming operation which includes program verification. This is especially true when a large segment, such as multiple bytes, of the memory is to be programmed. The present invention greatly simplifies such programming operations, particularly in those applications where a large segment of memory is to be programmed. This and other advantages of the present invention will be apparent to those skilled in the art upon a reading of the following Description of the Preferred Embodiment together with the drawings.
As previously noted, data systems incorporating memory systems having multiple memory devices are well known. By way of example, FIG. 1 depicts a simplified conventional memory system which includes a host device 20, an address decoder 22 and memory devices 24A and 24B. The host device 22 may be a microprocessor and the memory devices 24A and 24B may be separate memory integrated circuits. An address bus 26 is used to provide addresses to an address decoder 22 and to the memory devices 24A and 24B. The address decoder 22 has two outputs connected to enable inputs of the memory devices 24A and 24B. Typically, the most significant bit(s) of the address are provided on the bus 26 to the decoder 22, with the remaining address bits being provided to each of the memory devices.
When memory is to be accessed, the processor 20 causes the address decoder 22 to decode the most significant bit(s) of the memory address placed on an address bus 26. The decoder 22 will select one of the two memory devices 24A and 24B by generating either signal Sel 0 or Sel 1. The selected memory device will respond to the address presented to it on the address bus and the deselected memory device, which is disabled, will not respond. Although not shown, a data bus is used to transfer data between the memory devices and the processor 20, with only the selected device outputting data to the data bus during memory read operations.
The approach depicted in FIG. 1 is sometimes referred to as radial device selection where each memory device has a separate select input. This approach works well when relatively few memory devices are employed and where access speed, particularly random access speed, is important. However, if a large number of memory devices are used so that large amounts of data can be stored, the requirement of separate select lines for each memory device results in large memory boards and a relatively large pin count for the control logic circuitry. Thus, unless access speed is critical and a large number of memory devices are used, the radial device selection approach of FIG. 1 is not ideal.
FIG. 2 shows an alternative prior art device selection technique, sometimes referred to as serial selection. Again, a host device 28 is used which is connected to several memory devices 30A, 30B and 30C by way of a system bus 32. The memory devices 30A, 30B and 30C are usually implemented as separate integrated circuits. The system bus 32 includes memory address and memory data and various control signals so that each of the memory devices 30A, 30B 30C receives the same addresses, data and other signals. Each memory device is preassigned a unique address so that only one device will be accessed by the host device 28 during a memory operation. Typically, the memory devices 30A, 30B and 30C are assigned addresses by way of jumper or switch settings represented by elements 34A, 34B and 34C.